Modeling and Design of Low-Voltage Ferroelectric Memories.POMPES PAR TRANSITIONS MULTIPLES

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" Modeling and Design of Low-Voltage Ferroelectric Memories.POMPES PAR TRANSITIONS MULTIPLES "

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	154592
Doc. No	:	ET26384
Main Entry	:	Jeffery Chow
Title Proper	:	Modeling and Design of Low-Voltage Ferroelectric Memories.POMPES PAR TRANSITIONS MULTIPLES
Note	:	This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract	:	The migration of FeRAMYs to low operating voltages (1V and below) is resulting in newchallenges in the modeling and design of ferroelectric memories. This thesis presents aVerilog-A model that accounts for the voltage-dependent switching-time (VDST) offerroelectric capacitors evident at low voltages. The VDST Model is adaptable to.
Subject	:	Electericl tess
	:	برق
electronic file name	:	TL50657.pdf
Title and statement of responsibility and	:	Modeling and Design of Low-Voltage Ferroelectric Memories.POMPES PAR TRANSITIONS MULTIPLES [Thesis]