ON-CHIP SELF-TEST CIRCUIT BLOCKS FOR HIGH-SPEED APPLICATIONS.POMPES PAR TRANSITIONS MULTIPLES

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" ON-CHIP SELF-TEST CIRCUIT BLOCKS FOR HIGH-SPEED APPLICATIONS.POMPES PAR TRANSITIONS MULTIPLES "

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	154586
Doc. No	:	ET26378
Main Entry	:	Ekaterina Laskin
Title Proper	:	ON-CHIP SELF-TEST CIRCUIT BLOCKS FOR HIGH-SPEED APPLICATIONS.POMPES PAR TRANSITIONS MULTIPLES
Note	:	This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract	:	In this thesis, the advantages of parallel pseudo-random bit sequence (PRBS) generators forhigh-speed self-test applications are examined. An ultra-low-power, 4-channel 27 - 1 PRBSgenerator with 60 mW per channel was designed, fabricated and measured to work correctlyup to 23 Gbls. The circuit was based on a 12-Gbls, 2.5-mW BiCMOS current-mode logic.
Subject	:	Electericl tess
	:	برق
electronic file name	:	TL50651.pdf
Title and statement of responsibility and	:	ON-CHIP SELF-TEST CIRCUIT BLOCKS FOR HIGH-SPEED APPLICATIONS.POMPES PAR TRANSITIONS MULTIPLES [Thesis]