FPGA Implementation of Congestion Control Routers in High Speed Networks.POMPES PAR TRANSITIONS MULTIPLES

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" FPGA Implementation of Congestion Control Routers in High Speed Networks.POMPES PAR TRANSITIONS MULTIPLES "

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	154022
Doc. No	:	ET25814
Main Entry	:	Fariborz Fereydouni-Forouzandeh
Title Proper	:	FPGA Implementation of Congestion Control Routers in High Speed Networks.POMPES PAR TRANSITIONS MULTIPLES
Note	:	This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract	:	Receiving large number of data packets at different baud rates and differentsizes at gateways in high-speed network routers may lead to a congestionproblem and force the gateway to drop some packets. Several algorithms havebeen developed to control this problem. Among them the Random.
Subject	:	Electericl tess
	:	برق
electronic file name	:	TL50083.pdf
Title and statement of responsibility and	:	FPGA Implementation of Congestion Control Routers in High Speed Networks.POMPES PAR TRANSITIONS MULTIPLES [Thesis]