IP Protection for DSP Algorithms' FPGA Implementation.POMPES PAR TRANSITIONS MULTIPLES

منو

" IP Protection for DSP Algorithms' FPGA Implementation.POMPES PAR TRANSITIONS MULTIPLES "

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	153749
Doc. No	:	ET25541
Main Entry	:	Wei Dai
Title Proper	:	IP Protection for DSP Algorithms' FPGA Implementation.POMPES PAR TRANSITIONS MULTIPLES
Note	:	This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract	:	With today's system-on-chip (SOC) technology, we are able to design larger andmore complicated application-specific integrated circuits (ASICs) and fieldprogrammable gate array (FPGA) in shorter time period. The key point of thesuccess of SOC technology is the reuse of intellectual property (IP) cores.Consequently the copyright protection for these IP cores becomes the major concernfor the development pace of SOC technology..
Subject	:	Electericl tess
	:	برق
electronic file name	:	TL49799.pdf
Title and statement of responsibility and	:	IP Protection for DSP Algorithms' FPGA Implementation.POMPES PAR TRANSITIONS MULTIPLES [Thesis]