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Document Type : Latin Dissertation
Language of Document : English
Record Number : 152271
Doc. No : ET24063
Main Entry : HAYDAR KUTUK
Title Proper : A FAST TIMING SIMULATOR WITH ACCURATE REDUCED-ORDER INTERCONNECT MODELS
Note : This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract : In this research, we investigated techniques to simulate RLCG interconnects alongwith driving/terminating nonlinear circuits with high computational efficiency. Esist-ing fast timing simulators have the shortcomings of inadequate modeling of interc-on-nect loading and lack of inductive effects. Especially with shrinking device sizrr t heinterconnects are playing a more important role t t~an ever. It is a well accepted Factthat interconnect lengths are not going to decrease: hence, interconnect.
Subject : Electericl tess
: برق
electronic file name : TL48219.pdf
Title and statement of responsibility and : A FAST TIMING SIMULATOR WITH ACCURATE REDUCED-ORDER INTERCONNECT MODELS [Thesis]
 
 
 
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