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Document Type : Latin Dissertation
Language of Document : English
Record Number : 151713
Doc. No : ET23505
Main Entry : Gaurishankar Govindaraju
Title Proper : APPROXIMATE SYMBOLIC MODEL CHECKING USING OVERLAPPING PROJECTIONS
Note : This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract : Bugs in hardware cost money. Whenever an error creeps into a design, time andmoney must be spent to locate the problem and correct it. With the growing complex-ity of digital systems, and the tremendous pressure for early-time-to-market schedules,the need for verification tools that can help designers catch bugs at an early stage inthe design process cannot be overemphasized.Traditional methods of verification are empirical in nature and are based on ex-tensive simulation of hand-written or automatically generated diagnostic test vectors.Although provably effective in the early stages of the debugging process, their effec-tiveness drops quickly as the size of the state space grows larger. There has beenextensive research on more formal methods based on the use of theorem provers tocomprehensively verify designs. But these techniques are time consuming and oftenrequire a great deal of human espertise to construct a detailed logical proof.......-....,....-...,..tested for theQ1 PC1 bus cardBoth these projects mere sofixare des elopment efforts tonards contributing to dlfferentaspects of Roboucs and lZ1echatronics projects m the Controls and Roboucs Group..
Subject : Electericl tess
: برق
electronic file name : TL46746.pdf
Title and statement of responsibility and : APPROXIMATE SYMBOLIC MODEL CHECKING USING OVERLAPPING PROJECTIONS [Thesis]
 
 
 
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