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Document Type : Latin Dissertation
Language of Document : English
Record Number : 149927
Doc. No : ET21719
Main Entry : SURYANARAYANA BHIMESHWARA TATAPUDI
Title Proper : A HIGH PERFORMANCE LOW POWER MESOCHRONOUS PIPELINE ARCHITECTURE FOR COMPUTER SYSTEMS
Note : This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract : In a conventional pipeline scheme each pipeline stage operates on only one data set at atime. The clock period in conventional pipeline scheme is proportional to the maximumpipeline stage delay. We propose a mesochronous pipeline scheme, where pipeline stagesoperate on multiple data sets simultaneously. In this scheme the amount of logic in astage is more and number of stages is less compared to a conventional pipeline. The clockperiod in this scheme is proportional to the maximum pipeline stage delay difference,which means higher clock speeds are possible and number of pipeline stages issignificantly less. In mesochronous pipeline scheme, clock distribution network is simpleand load on it is less. A detailed analysis of the clock period constraints is provided toshow the performance gain and Speedup of mesochronous pipelining over otherpipelining schemes. In mesochronous pipeline..tested for theQ1 PC1 bus cardBoth these projects mere sofixare des elopment efforts tonards contributing to dlfferentaspects of Roboucs and lZ1echatronics projects m the Controls and Roboucs Group..
Subject : Electericl tess
: برق
electronic file name : TL44901.pdf
Title and statement of responsibility and : A HIGH PERFORMANCE LOW POWER MESOCHRONOUS PIPELINE ARCHITECTURE FOR COMPUTER SYSTEMS [Thesis]
 
 
 
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