INTEGRATED CIRCUIT METROLOGY BY MULTILEVEL PATTERNING TECHNOLOGY

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" INTEGRATED CIRCUIT METROLOGY BY MULTILEVEL PATTERNING TECHNOLOGY "

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	149877
Doc. No	:	ET21669
Main Entry	:	Li Jiang
Title Proper	:	INTEGRATED CIRCUIT METROLOGY BY MULTILEVEL PATTERNING TECHNOLOGY
Note	:	This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract	:	A low cost, high accuracy method is described in detail for measuring imageplacement in integrated circuit manufacture. The method measures both the overlaybetween levels and the absolute placement of features in a single level. The overlay ismeasured by a technique which views multiple levels separately. The absolute distancesbetween features on a test wafer are measured by comparing the features to precisiongratings. Optical imaging techniques are described for viewing and analyzing the gratingimages, as well as for measuring distortions in the observing microscope and a videocamera. These techniques permit image placement measurements to be made to anaccuracy limited by that of available gratings, at present about 2 nm. In addition they..tested for theQ1 PC1 bus cardBoth these projects mere sofixare des elopment efforts tonards contributing to dlfferentaspects of Roboucs and lZ1echatronics projects m the Controls and Roboucs Group..
Subject	:	Electericl tess
	:	برق
electronic file name	:	TL44849.pdf
Title and statement of responsibility and	:	INTEGRATED CIRCUIT METROLOGY BY MULTILEVEL PATTERNING TECHNOLOGY [Thesis]