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Document Type : Latin Dissertation
Language of Document : English
Record Number : 148733
Doc. No : ET20525
Main Entry : RAGHVENDRA UPADHYAY
Title Proper : FRAMEWORK OF SOFTWARE AGENT BASED ENVIRONMENT FOR LINKING DISTRIBUTIVE SIMULATION OF VERILOG
Note : This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract : As integrated circuits are becoming more dense and complex, the simulationspeed has become a bottleneck in the verification process. Verification engineers are inneed of some simulation techniques that can speed up the process.In this thesis, I present a framework to optimize the simulation time, by.
Subject : Electericl tess
: برق
electronic file name : TL43662.pdf
Title and statement of responsibility and : FRAMEWORK OF SOFTWARE AGENT BASED ENVIRONMENT FOR LINKING DISTRIBUTIVE SIMULATION OF VERILOG [Thesis]
 
 
 
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