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| Document Type
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Latin Dissertation
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| Language of Document
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English
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| Record Number
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148733
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| Doc. No
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ET20525
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| Main Entry
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RAGHVENDRA UPADHYAY
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| Title Proper
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FRAMEWORK OF SOFTWARE AGENT BASED ENVIRONMENT FOR LINKING DISTRIBUTIVE SIMULATION OF VERILOG
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| Note
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This document is digital این مدرک بصورت الکترونیکی می باشد
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| Abstract
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As integrated circuits are becoming more dense and complex, the simulationspeed has become a bottleneck in the verification process. Verification engineers are inneed of some simulation techniques that can speed up the process.In this thesis, I present a framework to optimize the simulation time, by.
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| Subject
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Electericl tess
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برق
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| electronic file name
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TL43662.pdf
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| Title and statement of responsibility and
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FRAMEWORK OF SOFTWARE AGENT BASED ENVIRONMENT FOR LINKING DISTRIBUTIVE SIMULATION OF VERILOG [Thesis]
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http://lib.khuisf.ac.ir/site/catalogue/148733
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