DESIGN OF CMOS INTEGRATED PHASE-LOCKED LOOPS FOR MULTI-GIGABITS SERIAL DATA LINKS

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" DESIGN OF CMOS INTEGRATED PHASE-LOCKED LOOPS FOR MULTI-GIGABITS SERIAL DATA LINKS "

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	148580
Doc. No	:	ET20372
Main Entry	:	SHANFENG CHENG
Title Proper	:	DESIGN OF CMOS INTEGRATED PHASE-LOCKED LOOPS FOR MULTI-GIGABITS SERIAL DATA LINKS
Note	:	This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract	:	High-speed serial data links are quickly gaining in popularity and replacing theconventional parallel data linlts in recent years when the data rate of communicationexceeds one gigabits per second. Compared with parallel data links, serial data linlts areable to achieve higher data rate and longer transfer distance. This dissertation is focused onthe design of CMOS integrated phase-locked loops (PLLs) and relevant building blocksused in multi-gigabits serial data link transceivers..
Subject	:	Electericl tess
	:	برق
electronic file name	:	TL43499.pdf
Title and statement of responsibility and	:	DESIGN OF CMOS INTEGRATED PHASE-LOCKED LOOPS FOR MULTI-GIGABITS SERIAL DATA LINKS [Thesis]