Optimizing Power, Delay and Reliability for Digital Logic Circuits with CMOS and Single-Electron TechnologiesET C A L I B ~ &RIQUEMENTET C A L I B ~&RIQUEMENT.POMPES PAR TRANSITIONS MULTIPLES

منو

" Optimizing Power, Delay and Reliability for Digital Logic Circuits with CMOS and Single-Electron TechnologiesET C A L I B ~ &RIQUEMENTET C A L I B ~&RIQUEMENT.POMPES PAR TRANSITIONS MULTIPLES "

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	154649
Doc. No	:	ET26441
Main Entry	:	Jialin Mi
Title Proper	:	Optimizing Power, Delay and Reliability for Digital Logic Circuits with CMOS and Single-Electron TechnologiesET C A L I B ~ RIQUEMENTET C A L I B ~RIQUEMENT.POMPES PAR TRANSITIONS MULTIPLES
Note	:	This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract	:	In this thesis, we present two low power approaches with consideration of delay and/orreliability. The first approach is based on CMOS (Complementary Metal-OxideSemiconductor) technology. Given a gate level topology of digital circuits and a targetlibrary, we propose a greedy algorithm for delay budgeting in order to optimize power.
Subject	:	Electericl tess
	:	برق
electronic file name	:	TL50714.pdf
Title and statement of responsibility and	:	Optimizing Power, Delay and Reliability for Digital Logic Circuits with CMOS and Single-Electron TechnologiesET C A L I B ~ RIQUEMENTET C A L I B ~RIQUEMENT.POMPES PAR TRANSITIONS MULTIPLES [Thesis]