INTERFACE TIMING VERIFICATION USING CONSTRAINT LOGIC PROGRAMMING AND BINARY DECISION DIAGRAMS.POMPES PAR TRANSITIONS MULTIPLES

منو

" INTERFACE TIMING VERIFICATION USING CONSTRAINT LOGIC PROGRAMMING AND BINARY DECISION DIAGRAMS.POMPES PAR TRANSITIONS MULTIPLES "

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	154378
Doc. No	:	ET26170
Main Entry	:	Albina Shapiro
Title Proper	:	INTERFACE TIMING VERIFICATION USING CONSTRAINT LOGIC PROGRAMMING AND BINARY DECISION DIAGRAMS.POMPES PAR TRANSITIONS MULTIPLES
Note	:	This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract	:	The design and verification of high performance circuits is becoming increasinglychallenging due to the complex sets of constraints that must hold to ensure correctoperation. The complexity of digital circuits increases rapidly, which in turn results in anincreased complexity of the verification process and increased user effort. Efficient andeasy to use tools are therefore required for timed verification..
Subject	:	Electericl tess
	:	برق
electronic file name	:	TL50443.pdf
Title and statement of responsibility and	:	INTERFACE TIMING VERIFICATION USING CONSTRAINT LOGIC PROGRAMMING AND BINARY DECISION DIAGRAMS.POMPES PAR TRANSITIONS MULTIPLES [Thesis]