CURRENT MODE LOGIC LATCH AND PRESCALER DESIGN OPTIMIZATION IN 0.18pm CMOS TECHNOLOGY.POMPES PAR TRANSITIONS MULTIPLES

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" CURRENT MODE LOGIC LATCH AND PRESCALER DESIGN OPTIMIZATION IN 0.18pm CMOS TECHNOLOGY.POMPES PAR TRANSITIONS MULTIPLES "

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	154137
Doc. No	:	ET25929
Main Entry	:	MUHAMMAD YUSAMA
Title Proper	:	CURRENT MODE LOGIC LATCH AND PRESCALER DESIGN OPTIMIZATION IN 0.18pm CMOS TECHNOLOGY.POMPES PAR TRANSITIONS MULTIPLES
Note	:	This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract	:	This thesis begins with a discussion of clocked storage elements in general, andthen narrows its focus to current-mode logic (CML) after simulation results for high speedapplications have been considered. Emphasis is given to the more important circuit charac-teristics, especially those involving timing and metastable behavior..
Subject	:	Electericl tess
	:	برق
electronic file name	:	TL50201.pdf
Title and statement of responsibility and	:	CURRENT MODE LOGIC LATCH AND PRESCALER DESIGN OPTIMIZATION IN 0.18pm CMOS TECHNOLOGY.POMPES PAR TRANSITIONS MULTIPLES [Thesis]