Modeling and Evaluation of a Hierarchical Ring Interconnect for System-on-Chip Multiprocessing.POMPES PAR TRANSITIONS MULTIPLES

منو

" Modeling and Evaluation of a Hierarchical Ring Interconnect for System-on-Chip Multiprocessing.POMPES PAR TRANSITIONS MULTIPLES "

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	154117
Doc. No	:	ET25909
Main Entry	:	Benjamin S. Kuo
Title Proper	:	Modeling and Evaluation of a Hierarchical Ring Interconnect for System-on-Chip Multiprocessing.POMPES PAR TRANSITIONS MULTIPLES
Note	:	This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract	:	This thesis proposes a software model for a multiprocessor system, which is targeted for SoCimplementation. The proposed design is based on the two-level ring architecture adopted inthe NUMAchine multiprocessor developed at University of Toronto. The proposed system re-considers the interconnect design alternatives for smaller design area and energy consumption.The system uses an alternative memory architecture to reduce logic complexity, as well as a.
Subject	:	Electericl tess
	:	برق
electronic file name	:	TL50181.pdf
Title and statement of responsibility and	:	Modeling and Evaluation of a Hierarchical Ring Interconnect for System-on-Chip Multiprocessing.POMPES PAR TRANSITIONS MULTIPLES [Thesis]