Architecture and Circuit Techniques for a 2 GHz Advanced High-speed Bus SoC Interconnect Infrastructure.POMPES PAR TRANSITIONS MULTIPLES

منو

" Architecture and Circuit Techniques for a 2 GHz Advanced High-speed Bus SoC Interconnect Infrastructure.POMPES PAR TRANSITIONS MULTIPLES "

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	154033
Doc. No	:	ET25825
Main Entry	:	Alexandre Landry
Title Proper	:	Architecture and Circuit Techniques for a 2 GHz Advanced High-speed Bus SoC Interconnect Infrastructure.POMPES PAR TRANSITIONS MULTIPLES
Note	:	This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract	:	A key issue with high performance SoC platforms is how to interconnect theirmodules to effectively transfer large amounts of data in real-time. Today's most practicalcommunication infrastructures are bus-based due to the small number of processingelements residing on a silicon die. Since the bandwidth of a shared bus goes down.
Subject	:	Electericl tess
	:	برق
electronic file name	:	TL50094.pdf
Title and statement of responsibility and	:	Architecture and Circuit Techniques for a 2 GHz Advanced High-speed Bus SoC Interconnect Infrastructure.POMPES PAR TRANSITIONS MULTIPLES [Thesis]