EXTRACTION ERROR MODELLING AND AUTOMATEDEBUGGING IN HIGH PERFORMANCE CUSTOM DESIGNS.POMPES PAR TRANSITIONS MULTIPLES

منو

" EXTRACTION ERROR MODELLING AND AUTOMATEDEBUGGING IN HIGH PERFORMANCE CUSTOM DESIGNS.POMPES PAR TRANSITIONS MULTIPLES "

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	153715
Doc. No	:	ET25507
Main Entry	:	Yu-Shen Yang
Title Proper	:	EXTRACTION ERROR MODELLING AND AUTOMATEDEBUGGING IN HIGH PERFORMANCE CUSTOM DESIGNS.POMPES PAR TRANSITIONS MULTIPLES
Note	:	This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract	:	Test model generation is a crucial step in the design cycle of high performance VLSIcircuits. A key step in test model generation is logic extraction, which generates a gate-level netlist from a transistor-level design. Logic extraction is error-prone due to human.
Subject	:	Electericl tess
	:	برق
electronic file name	:	TL49763.pdf
Title and statement of responsibility and	:	EXTRACTION ERROR MODELLING AND AUTOMATEDEBUGGING IN HIGH PERFORMANCE CUSTOM DESIGNS.POMPES PAR TRANSITIONS MULTIPLES [Thesis]