On-Chip Global Interconnect OptimizationPOMPES PAR TRANSITIONS MULTIPLES

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" On-Chip Global Interconnect OptimizationPOMPES PAR TRANSITIONS MULTIPLES "

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	153200
Doc. No	:	ET24992
Main Entry	:	Mourad Oulmane,
Title Proper	:	On-Chip Global Interconnect OptimizationPOMPES PAR TRANSITIONS MULTIPLES
Note	:	This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract	:	We present a practical yet accurate approach for dealing with the problem ofinserting repeaters along on-chip interconnect lines to meet delay and transition timerequirements. This approach is based on the fact that the transition time and the delay atthe far end of an interconnect segment are, respectively,.
Subject	:	Electericl tess
	:	برق
electronic file name	:	TL49206.pdf
Title and statement of responsibility and	:	On-Chip Global Interconnect OptimizationPOMPES PAR TRANSITIONS MULTIPLES [Thesis]