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" HIGH-LEVEL CLOCK CONSTRUCTION FOR LOW POWERPOMPES PAR TRANSITIONS MULTIPLES "


Document Type : Latin Dissertation
Language of Document : English
Record Number : 153086
Doc. No : ET24878
Main Entry : Changjun Kang
Title Proper : HIGH-LEVEL CLOCK CONSTRUCTION FOR LOW POWERPOMPES PAR TRANSITIONS MULTIPLES
Note : This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract : Clock network is the heaviest load in synchronous VLSl systems. It accounts for largeportion of the tow power dissipation. Our work concentrates on high-level optimization of the powerof clock network, which is a relatively new area. Our work includes two parts: activity-sensitiveclock design for low power and low power clock based on clock frequency reduction..
Subject : Electericl tess
: برق
electronic file name : TL49089.pdf
Title and statement of responsibility and : HIGH-LEVEL CLOCK CONSTRUCTION FOR LOW POWERPOMPES PAR TRANSITIONS MULTIPLES [Thesis]
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TL49089.pdf
TL49089.pdf
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