A 10 Gb/s CDRIDEMUX with LC Delay Line VCO in 0.18pm CMOSPOMPES PAR TRANSITIONS MULTIPLES

منو

" A 10 Gb/s CDRIDEMUX with LC Delay Line VCO in 0.18pm CMOSPOMPES PAR TRANSITIONS MULTIPLES "

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	153055
Doc. No	:	ET24847
Main Entry	:	Jonathan E. Rogers
Title Proper	:	A 10 Gb/s CDRIDEMUX with LC Delay Line VCO in 0.18pm CMOSPOMPES PAR TRANSITIONS MULTIPLES
Note	:	This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract	:	A monolithic LO Gbls clock/data recovery and 1 2 demultiplexer is implemented in 0.18pmCMOS. The quadrature LC delay line oscillator has a tuning range of 125 MHz and a 60 MHzNsensitivity to power supply pulling. The circuit meets SONET OC- 192 jitter specifications with ameasured jitter of ips rms when locked to a 2.5GHz sinusoidal reference. Clock and data recoveryis achieved at IOGbIs, demonstrating the feasibility of a half-rate earlyllate PD (with tri-state)based CDR in O.18pm CMOS. The 1 . 9 ~ 1 .5mm2 IC consumes 285mW (not including output buff-ers) from a 1.8V supply..
Subject	:	Electericl tess
	:	برق
electronic file name	:	TL49058.pdf
Title and statement of responsibility and	:	A 10 Gb/s CDRIDEMUX with LC Delay Line VCO in 0.18pm CMOSPOMPES PAR TRANSITIONS MULTIPLES [Thesis]