Design Considerations for High Speed Clock and Data Recovery CircuitsPOMPES PAR TRANSITIONS MULTIPLES

منو

" Design Considerations for High Speed Clock and Data Recovery CircuitsPOMPES PAR TRANSITIONS MULTIPLES "

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	152959
Doc. No	:	ET24751
Main Entry	:	Michel Beshara
Title Proper	:	Design Considerations for High Speed Clock and Data Recovery CircuitsPOMPES PAR TRANSITIONS MULTIPLES
Note	:	This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract	:	Design considerations for high speed clock and data recovery circuits are presented.Linear and bang-bang clock recovery architectures are examined and it is shown thatthe performance of the circuits is related to the performance of the flipflops used tobuild them. The design of high speed. emitter-coupled logic flipflops is investigated.
Subject	:	Electericl tess
	:	برق
electronic file name	:	TL48961.pdf
Title and statement of responsibility and	:	Design Considerations for High Speed Clock and Data Recovery CircuitsPOMPES PAR TRANSITIONS MULTIPLES [Thesis]