A GATE-LEVEL TIMING MODEL FOR SO1 CIRCUITSPOMPES PAR TRANSITIONS MULTIPLES

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" A GATE-LEVEL TIMING MODEL FOR SO1 CIRCUITSPOMPES PAR TRANSITIONS MULTIPLES "

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	152867
Doc. No	:	ET24659
Main Entry	:	Mehrdad Shahriari
Title Proper	:	A GATE-LEVEL TIMING MODEL FOR SO1 CIRCUITSPOMPES PAR TRANSITIONS MULTIPLES
Note	:	This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract	:	Partially depleted floating-body (PDFB) SO1 technology offers the potential ofincreased speed and lower power dissipation over traditional bulk CMOS. A key prob-lem, however, related to the use of traditional design flows for new SO1 designs is thatthe threshold voltage of the PDFB SO1 transistors and therefore the delay of logic.
Subject	:	Electericl tess
	:	برق
electronic file name	:	TL48868.pdf
Title and statement of responsibility and	:	A GATE-LEVEL TIMING MODEL FOR SO1 CIRCUITSPOMPES PAR TRANSITIONS MULTIPLES [Thesis]