MULTI-LEVEL LOGIC SYNTHESIS USING HYBRID PASS LOGIC AND CMOS TOPOLOGIESPOMPES PAR TRANSITIONS MULTIPLES

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" MULTI-LEVEL LOGIC SYNTHESIS USING HYBRID PASS LOGIC AND CMOS TOPOLOGIESPOMPES PAR TRANSITIONS MULTIPLES "

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	152772
Doc. No	:	ET24564
Main Entry	:	Kevin K.F. Yip, B.Sc(Eng)
Title Proper	:	MULTI-LEVEL LOGIC SYNTHESIS USING HYBRID PASS LOGIC AND CMOS TOPOLOGIESPOMPES PAR TRANSITIONS MULTIPLES
Note	:	This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract	:	For many digital designs, implementation in Pass Transistor Logic (PTL) is supe-rior to conventional static CMOS in terms of chip area. delay and power dissipation. How-ever, facing the problems with lacking a standard implementation methodology and very.
Subject	:	Electericl tess
	:	برق
electronic file name	:	TL48772.pdf
Title and statement of responsibility and	:	MULTI-LEVEL LOGIC SYNTHESIS USING HYBRID PASS LOGIC AND CMOS TOPOLOGIESPOMPES PAR TRANSITIONS MULTIPLES [Thesis]