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Document Type : Latin Dissertation
Language of Document : English
Record Number : 152650
Doc. No : ET24442
Main Entry : Ted S. Fill
Title Proper : An Assessment of VLSI and Embedded Software Implementations for Reed-Solomon DecodersPOMPES PAR TRANSITIONS MULTIPLES
Note : This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract : Reed-Solomon decoders are used extensively in numerous applications ranging from cellulartelephones to deep-space communications. This thesis examined Reed-Solomon time-domainand frequency-domain decoder implementations in both software and hardware. Thus far,there have been no clear, definitive statements in the published literature about the relativemerits and limitations of each type of decoder implementation. In response, a detailedcomparison is presented through tangible results from dedicated hardware and softwareimplementations. The focus was on designing area-efficient, low-power and low-complexitydecoders suitable for today's moderate rate applications. Two decoder chips were designed ina 0.18pm CMOS process and they targeted a decoding rate of 160 Mbps. The time-domaindecoder was fabricated and had a core area of 1.50 mm2 and an overall silicon die area of3.54 mm2..
Subject : Electericl tess
: برق
electronic file name : TL48649.pdf
Title and statement of responsibility and : An Assessment of VLSI and Embedded Software Implementations for Reed-Solomon DecodersPOMPES PAR TRANSITIONS MULTIPLES [Thesis]
 
 
 
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