On Synthesis and Optimization of Floating Point UnitsPOMPES PAR TRANSITIONS MULTIPLES

منو

" On Synthesis and Optimization of Floating Point UnitsPOMPES PAR TRANSITIONS MULTIPLES "

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	152541
Doc. No	:	ET24333
Main Entry	:	Syed Yawar AZi Shah
Title Proper	:	On Synthesis and Optimization of Floating Point UnitsPOMPES PAR TRANSITIONS MULTIPLES
Note	:	This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract	:	This work describes the effect of architecturaVsystem level design decisions on the perfor-mance of floating point arithmetic units. By modeling with VHDL and using design syn-thesis techniques, different architectures of floating point adders, multipliers and multiply- accumulate fused units, are compared using different technologies and cell libraries..
Subject	:	Electericl tess
	:	برق
electronic file name	:	TL48539.pdf
Title and statement of responsibility and	:	On Synthesis and Optimization of Floating Point UnitsPOMPES PAR TRANSITIONS MULTIPLES [Thesis]