VHDL DESIGN AND IMPLEMENTATION OF A LAN ON A CHIPPOMPES PAR TRANSITIONS MULTIPLES

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" VHDL DESIGN AND IMPLEMENTATION OF A LAN ON A CHIPPOMPES PAR TRANSITIONS MULTIPLES "

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	152503
Doc. No	:	ET24295
Main Entry	:	Xiao Gang Deng
Title Proper	:	VHDL DESIGN AND IMPLEMENTATION OF A LAN ON A CHIPPOMPES PAR TRANSITIONS MULTIPLES
Note	:	This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract	:	With ever increasing usage of Internet and more demand for real-time applications, theintrinsic shortcoming of Ethernet becomes more and more apparent. Ethernetarchitecture combined with the Medium Access Control protocol can not guarantee amaximum time delay variation, jitter, which Es critical to real-time appIications. In thisthesis, a novel LAN architecture is proposed, designed and implemented with fieldprogrammable gate array (FPGA) device as target. This LAN on a chip &sign issimple, scaleable and modular. The preliminary simulation shows that it reduces theimpact of packet collision on the LAN and improves the pe-iforrnance in terms ofreducing and limiting jitter on real-time traffic..
Subject	:	Electericl tess
	:	برق
electronic file name	:	TL48501.pdf
Title and statement of responsibility and	:	VHDL DESIGN AND IMPLEMENTATION OF A LAN ON A CHIPPOMPES PAR TRANSITIONS MULTIPLES [Thesis]