Combined CMOS Decision Feedback Equalizer and Clock Data Recovery Circuit Design in Broadband Receivers

منو

" Combined CMOS Decision Feedback Equalizer and Clock Data Recovery Circuit Design in Broadband Receivers "

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	152188
Doc. No	:	ET23980
Main Entry	:	Lijun Li
Title Proper	:	Combined CMOS Decision Feedback Equalizer and Clock Data Recovery Circuit Design in Broadband Receivers
Note	:	This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract	:	With ever increasing high-speed link rates, the transmission path bandwidthbecomes severely limited by the dielectric loss, skin effect and impedance disconti-nuities of the copper cable and interconnects. To design robust, high-performancebroadband receivers, advanced equalization techniques are required to remove theintersymbol interference (ISI) due to these loss mechanisms. Because of the bet-ter noise performance, decision feedback equalizers (DFE) are preferred to analog.
Subject	:	Electericl tess
	:	برق
electronic file name	:	TL48126.pdf
Title and statement of responsibility and	:	Combined CMOS Decision Feedback Equalizer and Clock Data Recovery Circuit Design in Broadband Receivers [Thesis]