ANALYSIS, SIMULATION AND DESIGN OF LOW POWER FULL ADDER

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" ANALYSIS, SIMULATION AND DESIGN OF LOW POWER FULL ADDER "

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	151972
Doc. No	:	ET23764
Main Entry	:	PREETHI KUNDOOR
Title Proper	:	ANALYSIS, SIMULATION AND DESIGN OF LOW POWER FULL ADDER
Note	:	This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract	:	A single-bit full adder used in adding binary words is one of the main componentsin almost all logic structures. In this thesis performance analysis, simulation and designof a general 1-bit full adder cell are presented. The adder cell is anatomized into smallermodules using the proposed structured approach. The modules are studied extensivelyand several designs of each of them are shown. Connecting combinations of designs ofthese modules together, we construct 20 different 1-bit full adder cells (many of them arenovel circuits).Two circuit structures for simulating the adder cells based on the use of the addercell in bigger structures was chosen. Circuit.............-....,....-...,..tested for theQ1 PC1 bus cardBoth these projects mere sofixare des elopment efforts tonards contributing to dlfferentaspects of Roboucs and lZ1echatronics projects m the Controls and Roboucs Group..
Subject	:	Electericl tess
	:	برق
electronic file name	:	TL47023.pdf
Title and statement of responsibility and	:	ANALYSIS, SIMULATION AND DESIGN OF LOW POWER FULL ADDER [Thesis]