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Document Type : Latin Dissertation
Language of Document : English
Record Number : 151769
Doc. No : ET23561
Main Entry : Ali Saleh Mohammed Al-Suwaiyan
Title Proper : . Efficient Test Relaxation Techniques For Combinational Circuits
Note : This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract : The signijkant advancement in VtSrtechnology has made System-On-Chip (SOC) designs very popular: Oneofthe most chaflenging problems in testing SOCs is dealing with the large volume of test data- There havebeen two methods to release rhis problem, namely, test compaction and rest compression. Many compressiontechniques assume relaxed test set in order to achieve high compression ratios. In this work, we u&resx theproblem of generating a relaxed test set from a given test set- A Bitwise Relaxation (BR) technique can beused to solve this problem. However; the BR technique is very slow for large circuits. Another way to obtain arelaxed test set is to generate the test set using dynamic compaction technique, Dynamic compaction is slowas well, and generating the relued test set using this method slows down the ATPG process. Furthermore,dynamic compaction con not be used to relax an existing test set. Thus, the only existing solution to the testrelaxation problem is the BR method. In this work, we pmpose three eficient techniques to solve the testset relaxation problem. We also propose cost ficnctions to guide the selection in rnaximiir'ng the number ofextracted x's, The proposed techniques are fmter than the BR method by several orders of magnitude. Theyalso obtain comparable results with the BR method.......-....,....-...,..tested for theQ1 PC1 bus cardBoth these projects mere sofixare des elopment efforts tonards contributing to dlfferentaspects of Roboucs and lZ1echatronics projects m the Controls and Roboucs Group..
Subject : Electericl tess
: برق
electronic file name : TL46803.pdf
Title and statement of responsibility and : . Efficient Test Relaxation Techniques For Combinational Circuits [Thesis]
 
 
 
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