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Document Type : Latin Dissertation
Language of Document : English
Record Number : 151747
Doc. No : ET23539
Main Entry : Xian Hong Chen
Title Proper : Accurate Gate Delay Evaluation for CMOS Deep Sub-micron VLSl Circuits
Note : This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract : As CMOS processing technology advances into deep sub-micron (DSM) regime,resistive components of on-chip interconnect wire cause resistance shielding and non-linear signal waveform effects. As a result, the accuracy of timing analysis using aconventional gate delay modeling approach (single ramp input and lumped capacitanceload) is compromised. Resistance shielding effect on gate load can cause large gate delayoverestimate, and non-linear gate input signal can also result in significant gate delayerrors,In CMOS DSM VLSI circuits, gate load can be more accurately modeled as an RCtree and its second order approximation is an L-type K circuit.......-....,....-...,..tested for theQ1 PC1 bus cardBoth these projects mere sofixare des elopment efforts tonards contributing to dlfferentaspects of Roboucs and lZ1echatronics projects m the Controls and Roboucs Group..
Subject : Electericl tess
: برق
electronic file name : TL46780.pdf
Title and statement of responsibility and : Accurate Gate Delay Evaluation for CMOS Deep Sub-micron VLSl Circuits [Thesis]
 
 
 
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