Post-Compilation Analysis and Power Reduction

دانشگاه آزاد اسلامی اصفهان(خوراسگان)

منو

رکورد قبلی

رکورد بعدی

" Post-Compilation Analysis and Power Reduction "

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	151321
Doc. No	:	ET23113
Main Entry	:	Todd Waterman
Title Proper	:	Post-Compilation Analysis and Power Reduction
Note	:	This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract	:	Optimization outside of traditional frameworks is emerging as a new research focusin the compiler construction community. Scheduled assembly code is one area ofincreased interest. Optimization cannot be performed without a control-flow graph(CFG), and current CFG construction algorithms can fail on scheduled code. Wepresent a new construction algorithm that correctly constructs CFGs and permitsmeaningful optimization for scheduled code.One potential post-compilation optimization is reducing power consumption byminimizing switching activity on the instruction bus. We designed and implementedan algorithm that attempts to minimize switching activity by renaming registers forTexas Instruments' TMS320C6200 processor. We gathered results using a powersimulator developed inside Texas Instruments. We determine that reducing bit tran-sitions on the instruction bus is not a profitable technique for reducing the powerconsumption of this particular microprocessor..-....,....-...,..tested for theQ1 PC1 bus cardBoth these projects mere sofixare des elopment efforts tonards contributing to dlfferentaspects of Roboucs and lZ1echatronics projects m the Controls and Roboucs Group..
Subject	:	Electericl tess
	:	برق
electronic file name	:	TL46347.pdf
Title and statement of responsibility and	:	Post-Compilation Analysis and Power Reduction [Thesis]