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Document Type : Latin Dissertation
Language of Document : English
Record Number : 151299
Doc. No : ET23091
Main Entry : ANAMA REDDY RAPOLU
Title Proper : FPGA ARCHITECTURE AND PERFORMANCE MEASUREMENT FOR FAST AREA EFFICIENT PARALLEL-PREFIX MODULO 2'01 ADDERS
Note : This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract : The Modulo adder is an instrumental arithmetic component in implementingonline residue-based computations for many digital signal processing applications. It isalso a basic component in realizing modular multipliers and residue to binary converters.Thus, the design of a high speed and reduced-area modular adder is an important issue.This thesis intends to implement fast area efficient Parallel-Prefix modulo 2n-1 adderusing the Xan-Carlson prefix structure and to compare it with the modified Kogge-Stone(KS) Parallel-Prefix modulo 2n--1 adder. The modulo adders would be simulated usingVHDL (Very High Speed Integrated Circuits Hardware Description Language) followedby an implementation on a FLEXlOK FPGA chip using MaxPlus II software..-....,....-...,..tested for theQ1 PC1 bus cardBoth these projects mere sofixare des elopment efforts tonards contributing to dlfferentaspects of Roboucs and lZ1echatronics projects m the Controls and Roboucs Group..
Subject : Electericl tess
: برق
electronic file name : TL46325.pdf
Title and statement of responsibility and : FPGA ARCHITECTURE AND PERFORMANCE MEASUREMENT FOR FAST AREA EFFICIENT PARALLEL-PREFIX MODULO 2'01 ADDERS [Thesis]
 
 
 
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