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Document Type : Latin Dissertation
Language of Document : English
Record Number : 151077
Doc. No : ET22869
Main Entry : Carlos Alberto Roman-Zayas
Title Proper : Exploiting Parallelism in a Vectorial Fingerprint Verification System
Note : This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract : Of all personal identification methods, those who rely on the use of biometrics havebeen proven to be the most reliable. Fingerprint verification is one of the least intrusivebiometrics based personal identification methods- However, manual fingerprint verification istoo time-consuming to be practical- The B iOmega Automatic Fingerprint Verification System(AFVS) has been developed in the University of Puerto Rico. The initial implementation wasdone utilizing the Matlab development environment. The results in terms of accuracy, FalseAcceptance Rate (FAR) and False Rejection Rate (FRR), have been very positive. But theperformance of the algorithms was too slow for a real-time application. After studying theinherent computing power necessary for image processing and analysis applications, it becameclear that in the manipulation of images the same computations are always carried, but fordifferent values of data. Because of this characteristic a symmetric multiprocessing computerwas considered the ideal platform for achieving the desired performance for the BiOrnegaAFVS, 1.0 seconds. Two parallel architectures where used in this research effort, thecommercially available Texas Insh-uments TMS320C80 and the SirnPil array processordeveloped by the Georgia Institute of Technology. Both architectures offer multiple processingunits in a single chip, and the advantage of local memory for each of the processing units. Thefocus of this research was to effectively translate the Matlab based BiOrnega AFVS into theselected platform to achieve the performance requirement of 1.0 seconds. The averagecomputation time for all the algorithms executed was 0.91 seconds. Image partition andmemory management were found to be important issues when trying to maximize processorutilization. But in both architectures the use of fixed point arithmetic instead of floating point..,....-...,..tested for theQ1 PC1 bus cardBoth these projects mere sofixare des elopment efforts tonards contributing to dlfferentaspects of Roboucs and lZ1echatronics projects m the Controls and Roboucs Group..
Subject : Electericl tess
: برق
electronic file name : TL46097.pdf
Title and statement of responsibility and : Exploiting Parallelism in a Vectorial Fingerprint Verification System [Thesis]
 
 
 
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