PERFORMANCE DRIVEN, LOW-POWER, STANDARD VLSI CELL PLACEMENT USING SIMULATED EVOLUTION

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" PERFORMANCE DRIVEN, LOW-POWER, STANDARD VLSI CELL PLACEMENT USING SIMULATED EVOLUTION "

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	151065
Doc. No	:	ET22857
Main Entry	:	JUI?JAID ASPM, KHAN
Title Proper	:	PERFORMANCE DRIVEN, LOW-POWER, STANDARD VLSI CELL PLACEMENT USING SIMULATED EVOLUTION
Note	:	This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract	:	In the last few years, research in VLSI physical CAD focused in the optimizationof area, wire-length and timing performance. These days research is also targetingtowards low power VLSI design. In this thesis, an algorithm for VLSI standard cellplacement for low power and high performance design is presented. This is a hardmultiobjective combinatorid optimization problem with no known exact and encientalgorithm that can guarantee finding a solution of specific or desirable quality. Ap-proximation iterative heuristics such as Simulated Evolution (SimE) are best suitedto perform an intelligent search of the solution space. SirnE comprises three steps,evaluation, selection and allocation. Due to imprecise nature of design informationat the placement stage the various objectives and constraints are expressed in fuzzydomain. The search is made to evolve towards a vector of fuzzy goals.In this work a new method to calculate membership in evaluation stage is pro-posed. Selection stage is also fuzzified. A new fuzzy operator is introduced. Theproposed heuristic is compared with other..,....-...,..tested for theQ1 PC1 bus cardBoth these projects mere sofixare des elopment efforts tonards contributing to dlfferentaspects of Roboucs and lZ1echatronics projects m the Controls and Roboucs Group..
Subject	:	Electericl tess
	:	برق
electronic file name	:	TL46084.pdf
Title and statement of responsibility and	:	PERFORMANCE DRIVEN, LOW-POWER, STANDARD VLSI CELL PLACEMENT USING SIMULATED EVOLUTION [Thesis]