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Document Type : Latin Dissertation
Language of Document : English
Record Number : 151002
Doc. No : ET22794
Main Entry : ANURADHA V. AMBATIPUDI
Title Proper : VLSI ARCHITECTURE OF A FAST BINARY ADDER WITH CONDITIONAL CARRY GENERATION
Note : This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract : Obtaining highest possible speed is one of the major concerns of computer design. Anadder plays an important role in the operations of a computer given that many of theALU's functions reduce to a simple addition or series of additions. The speed of theoverall machine is dependent on the speed of the ALU, which in turn is dependent on thespeed of the adder.An attempt was made to obtain a fast binary adder in this thesis. The 1 6-bit binaryadder is realized in 1.6pm static CMOS and is simulated using PSpice with circuitparameters provided by MOSIS. Its layout is drawn using Magic Iayout editor...,....-...,..tested for theQ1 PC1 bus cardBoth these projects mere sofixare des elopment efforts tonards contributing to dlfferentaspects of Roboucs and lZ1echatronics projects m the Controls and Roboucs Group..
Subject : Electericl tess
: برق
electronic file name : TL46020.pdf
Title and statement of responsibility and : VLSI ARCHITECTURE OF A FAST BINARY ADDER WITH CONDITIONAL CARRY GENERATION [Thesis]
 
 
 
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