خط مشی دسترسیدرباره ما
ثبت نامثبت نام
راهنماراهنما
فارسی
ورودورود
صفحه اصلیصفحه اصلی
جستجوی مدارک
تمام متن
منابع دیجیتالی
رکورد قبلیرکورد بعدی
Document Type : Latin Dissertation
Language of Document : English
Record Number : 150930
Doc. No : ET22722
Main Entry : SUMANTH NANDAGOPAL
Title Proper : PERFORMANCE IMPROVEMENT OF ARRAY MULTIPLIER USING TEMPORAL TILING
Note : This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract : Digital multipliers are a major source of power dissipation in digital signal processors. Arrayarchitecture is a popular technique to implement these multipliers due to its compact structure.High power dissipation in the structure is mainly due to the switching of a large number of gatesduring multiplication and also due to a large number of spurious transitions on internal nodes.The timing analysis of full adders and the basic building blocks of the array multiplier haveresulted in a different array connection pattern that reduces power dissipation due to spurioustransitions. This array pattern is based on creating a compact tiled structure. This thesis intendsto compare the delays of the temporally tiled array multiplier with the conventional arraymultiplier. This is accomplished by creating an overall delay-balanced structure from the existingcomponents with the delay imbalances.,....-...,..tested for theQ1 PC1 bus cardBoth these projects mere sofixare des elopment efforts tonards contributing to dlfferentaspects of Roboucs and lZ1echatronics projects m the Controls and Roboucs Group..
Subject : Electericl tess
: برق
electronic file name : TL45948.pdf
Title and statement of responsibility and : PERFORMANCE IMPROVEMENT OF ARRAY MULTIPLIER USING TEMPORAL TILING [Thesis]
 
 
 
(در صورت عدم وضوح تصویر اینجا را کلیک نمایید)