EDIF Net list Optimization of Pipelined Designs

دانشگاه آزاد اسلامی اصفهان(خوراسگان)

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" EDIF Net list Optimization of Pipelined Designs "

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	150890
Doc. No	:	ET22682
Main Entry	:	Vasileios Balabanos
Title Proper	:	EDIF Net list Optimization of Pipelined Designs
Note	:	This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract	:	This thesis describes the design, implementation, and evaluation of a software system foroptimizing synthesized logic circuits. The particular implementation described is targetedto the Xilinx Virtex family of FPGAs, but the techniques developed are relevant to otherfamilies of may-based semi-custom programmable logic circuits. One of the uniqueaspects of my approach is that the optimization occurs after the circuit is mapped onto thelogic array. Prior to this work it was commonly believed that optimization after mappingwas infeasible. The advantages of this approach include the ability to optimize a designwithout having the VHDL source code, the opportunity to selectively optimize only partsof a circuit and the preservation of the original the state encoding. The optimizations arealso transparent to the synthesis process. This is a powerful and versatile method, whichgives the designer considerable freedom in optimizing parts of the design according to hisor her preferences.The optimization process proceeds as follows. The behavioral or structural description ofthe design is first written in VHDL. The design is then synthesized using the WorkviewOffice synthesis tool and extracted to an EDIF (Electronic Design Interface Format)mapped netlist targeting Xilinx's Vinex family of FPGAs. This netlist is then analyzed,and an internal representation of the given circuit is created. Any pipelines (blocks ofcombinational logic feeding one or more registers) that exist in the circuit are then....-...,..tested for theQ1 PC1 bus cardBoth these projects mere sofixare des elopment efforts tonards contributing to dlfferentaspects of Roboucs and lZ1echatronics projects m the Controls and Roboucs Group..
Subject	:	Electericl tess
	:	برق
electronic file name	:	TL45908.pdf
Title and statement of responsibility and	:	EDIF Net list Optimization of Pipelined Designs [Thesis]