EFFICIENT STATIC TEST COMPACTION ALGORITHMS FOR COMBINATIONAL CIRCUITS BASED ON TEST RELAXATION

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" EFFICIENT STATIC TEST COMPACTION ALGORITHMS FOR COMBINATIONAL CIRCUITS BASED ON TEST RELAXATION "

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	150639
Doc. No	:	ET22431
Main Entry	:	YAHYA ESMAIL OSAIS
Title Proper	:	EFFICIENT STATIC TEST COMPACTION ALGORITHMS FOR COMBINATIONAL CIRCUITS BASED ON TEST RELAXATION
Note	:	This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract	:	Advances in the semi-conductor process and design technology have paved the wayfor system-on-chips (SoCs). Traditional IC design in which every circuit is designedfrom scratch and reuse is limited only to standard cell libraries is more and more re-placed by the SoC design methodology. However, this new design methodology hasits own challenges. A major challenge is to reduce the increasing volume of test data.Basically, there are two approaches: compression and compaction. In this thesis, theproblems of static compaction and test vector reordering for combinational circuitsare investigated. A new class of static compaction....-...,..tested for theQ1 PC1 bus cardBoth these projects mere sofixare des elopment efforts tonards contributing to dlfferentaspects of Roboucs and lZ1echatronics projects m the Controls and Roboucs Group..
Subject	:	Electericl tess
	:	برق
electronic file name	:	TL45647.pdf
Title and statement of responsibility and	:	EFFICIENT STATIC TEST COMPACTION ALGORITHMS FOR COMBINATIONAL CIRCUITS BASED ON TEST RELAXATION [Thesis]