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Document Type : Latin Dissertation
Language of Document : English
Record Number : 150608
Doc. No : ET22400
Main Entry : Daniel A. Davis
Title Proper : Swathi Taniore Gururnani
Note : This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract : This thesis describes the major architecture features of an instruction setprocessor architecture that has been specifically developed to support the CommunicatingSequential Processes (CSP) paradigm. The processor architecture is fully described as anIntellectual Property (IP) soft core written in the V L hardware description languagewhere it can be used to create a single chip parallel processing environment, usingcommercially off the shelf, Field Programmable Gate Array (FPCA) technology. Unlikeother such IP cores that are present in the market place, this CSP-style core processorincorporates instruction set support for low latency high bandwidth synchronous messagepassing between similar core processors that reside within the same integrated circuit...-...,..tested for theQ1 PC1 bus cardBoth these projects mere sofixare des elopment efforts tonards contributing to dlfferentaspects of Roboucs and lZ1echatronics projects m the Controls and Roboucs Group..
Subject : Electericl tess
: برق
electronic file name : TL45610.pdf
Title and statement of responsibility and : Swathi Taniore Gururnani [Thesis]
 
 
 
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