A Design Study on the Scaling Limit of Ultra-Thin Silicon-on-Insulator MOSFETs

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" A Design Study on the Scaling Limit of Ultra-Thin Silicon-on-Insulator MOSFETs "

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	150357
Doc. No	:	ET22149
Main Entry	:	Wei-Yuan Lu
Title Proper	:	A Design Study on the Scaling Limit of Ultra-Thin Silicon-on-Insulator MOSFETs
Note	:	This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract	:	As bulk CMOS is approaching its scaling limit, SO1 CMOS is gaining moreand more attentions and is considered as a potential candidate for achieving 10-nmCMOS. Fully-depleted SO1 MOSFETs have several inherent advantages over bulkMOSFETs-low junction capacitance. no body effect and no need for body doping toconfine gate depletion. This dissertation presents a comprehensive, 2-D simulation-based design study on the scaling limit of ultra-thin silicon-on-insulator MOSFETs .xix...,..tested for theQ1 PC1 bus cardBoth these projects mere sofixare des elopment efforts tonards contributing to dlfferentaspects of Roboucs and lZ1echatronics projects m the Controls and Roboucs Group..
Subject	:	Electericl tess
	:	برق
electronic file name	:	TL45353.pdf
Title and statement of responsibility and	:	A Design Study on the Scaling Limit of Ultra-Thin Silicon-on-Insulator MOSFETs [Thesis]