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" Circuit Timing and Leakage Power Analysis Under Process Variations "


Document Type : Latin Dissertation
Language of Document : English
Record Number : 149836
Doc. No : ET21628
Main Entry : Hongliang Chang
Title Proper : Circuit Timing and Leakage Power Analysis Under Process Variations
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Abstract : The task of analyzing circuit performance has become very challenging in sub-lOOnm technologies due to the effects of numerous variations, particularly processvariations. Traditional multi-process-corner methods, which have been used to ac-count for these variations for many years, cannot be scaled to these technologiesas they become computationally expensive and over-pessimistic. Therefore, a sta-tistical approach to performance analysis must be developed in order to predictcircuit performance and yield more efficiently and accurately, and to guide circuitoptimization.In this thesis, we focus on the statistical analysis of timing and leakage power.Our approach considers both inter-die and intra-die process variations, as well asthe effect of spatial correlations,.tested for theQ1 PC1 bus cardBoth these projects mere sofixare des elopment efforts tonards contributing to dlfferentaspects of Roboucs and lZ1echatronics projects m the Controls and Roboucs Group..
Subject : Electericl tess
: برق
electronic file name : TL44805.pdf
Title and statement of responsibility and : Circuit Timing and Leakage Power Analysis Under Process Variations [Thesis]
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TL44805.pdf
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