POWER REDUCTION OF DIGITAL CIRCUIT BY INSERTING DELAY

منو

" POWER REDUCTION OF DIGITAL CIRCUIT BY INSERTING DELAY "

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	149536
Doc. No	:	ET21328
Main Entry	:	MANASAMEERA ADDA
Title Proper	:	POWER REDUCTION OF DIGITAL CIRCUIT BY INSERTING DELAY
Note	:	This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract	:	The objective of this thesis is to improve the power of CMOS digital circuit byinserting delay. CMOS technology is used to implement the logic gates of the digitalcircuits. Since, the dynamic power is the major source of power and it is directly relatedto signal transitions, it is advantageous to eliminate the unwanted transitions. Differentarrival times of the signals.
Subject	:	Electericl tess
	:	برق
electronic file name	:	TL44485.pdf
Title and statement of responsibility and	:	POWER REDUCTION OF DIGITAL CIRCUIT BY INSERTING DELAY [Thesis]