FPGA PROTOTYPING FOR FAST AND EFFICIENT VERIFICATION OF ASIC H.264 DECODER

منو

" FPGA PROTOTYPING FOR FAST AND EFFICIENT VERIFICATION OF ASIC H.264 DECODER "

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	149485
Doc. No	:	ET21277
Main Entry	:	BASAVARAJ MUDIGOUDAR
Title Proper	:	FPGA PROTOTYPING FOR FAST AND EFFICIENT VERIFICATION OF ASIC H.264 DECODER
Note	:	This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract	:	To improve compression efficiency, recent video compression standards such asH.264 use complex algorithms and various modes that demand more computationalpower. Consumer electronics industry requires a low power, compact and cost-effectiveimplementation of video codec for most of the products. ASIC implementation of these.
Subject	:	Electericl tess
	:	برق
electronic file name	:	TL44433.pdf
Title and statement of responsibility and	:	FPGA PROTOTYPING FOR FAST AND EFFICIENT VERIFICATION OF ASIC H.264 DECODER [Thesis]