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Document Type : Latin Dissertation
Language of Document : English
Record Number : 149353
Doc. No : ET21145
Main Entry : Sheng Sun
Title Proper : High Performance and Energy Efficient Adder Design
Note : This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract : This thesis consists of three closely related topics on high performance and energyefficient adder design. First, the author designed a high-speed 64b adder based on OutputPrediction Logic (OPL). It has a delay of 4.7 fanout-of-four (F04) inverter delays frommeasurement, compared to the best previously reported 6.8. Secondly, in order to verifythe timing of the 64b OPL adder, the author extended the WTA (Waveform-basedTiming Analysis) tool to handle OPL circuits. The new approach can achieve moreaccurate delay bounds than existing static timing analyzers at a computation cost that stillallows iterations between design modification and delay analysis. WTA analysis alsoenabled us to optimize the original.
Subject : Electericl tess
: برق
electronic file name : TL44293.pdf
Title and statement of responsibility and : High Performance and Energy Efficient Adder Design [Thesis]
 
 
 
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