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Document Type : Latin Dissertation
Language of Document : English
Record Number : 149317
Doc. No : ET21109
Main Entry : Nuttorn Jangkrajarng
Title Proper : AnalogIRF VLSI Layout Generation Layout Retargeting via Symbolic Template
Note : This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract : As technology scales down in transistor size, existing VLSI circuits can beredesigned for better performances and smaller areas. In a functional integratedsystems-on-a-chip, a new layout for a digital portion can be crafted automatically withindustrial-available tools based on an existing circuit schematic and a new standard-celllibrary. On the other hand, due to matching, parasitics, and substrate effects, an analogor RF layout portion generally has to be re-generated manually. Therefore, a fast andreliable parasitic-aware automatic layout generation for analog and RF circuits isinvented to retarget an existing layout to new processes and specifications. Based on alayout reuse, the method.
Subject : Electericl tess
: برق
electronic file name : TL44257.pdf
Title and statement of responsibility and : AnalogIRF VLSI Layout Generation Layout Retargeting via Symbolic Template [Thesis]
 
 
 
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