A Fast-Locking Frequency Synthesizer for GSM Base-stations in 180nm CMOS

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" A Fast-Locking Frequency Synthesizer for GSM Base-stations in 180nm CMOS "

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	149315
Doc. No	:	ET21107
Main Entry	:	Sankaran Aniruddhan
Title Proper	:	A Fast-Locking Frequency Synthesizer for GSM Base-stations in 180nm CMOS
Note	:	This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract	:	GSM Base-stations have extremely stringent phase noise and lock-time specifications due tosimultaneous communication with multiple mobile transceivers in a given range. Therefore,they are usually implemented using many off-chip components, especially the VCO. In thiswork, a 2GHz Dual-Loop-PLL architecture targeting this application is designed, fabricatedand tested. A fourth-harmonic mixer is applied in the feedback path of the main loop tosignificantly reduce the tuning range required of the reference loop. An auxiliary chargepump technique can be used to reduce the capacitance of the loop filter to manageablemonolithic values. Alternatively, an analogue of this technique is proposed to widen a givenloop bandwidth to enable a fast-lock mode in the PLL.The main loop employs a bondwire VCO, while the reference PLL contains a spiral-inductor-based VCO. Coarse tuning is utilized to account for process and bondwire inductancevariations. The analog and digital power supplies are separated as much as possible tominimize spur feedthrough. The reference PLL and main PLL use crystal frequencies of.
Subject	:	Electericl tess
	:	برق
electronic file name	:	TL44255.pdf
Title and statement of responsibility and	:	A Fast-Locking Frequency Synthesizer for GSM Base-stations in 180nm CMOS [Thesis]