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Document Type : Latin Dissertation
Language of Document : English
Record Number : 149104
Doc. No : ET20896
Main Entry : Manoj Kumar Goparaju
Title Proper : PARAMETRIC FAULT MODEL FOR LINEAR THRESHOLD LOGIC NETWORKS
Note : This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract : There is growing presence of Threshold Logic Gate in various VLSIimplementations owing to its reduced complexity, maneuverable at high frequencies andminimized wiring. Work has been done in the field of ATPG for CombinationalThreshold Logic Networks with emphasis on Stuck at fault model. In threshold logiccircuits with RTD-HFETs are principal elements. The characterstic of RTD-HFETgreatly depend on the parameters of RTD. But there is great chance of changes inparameters of RTD due to manufacturing.
Subject : Electericl tess
: برق
electronic file name : TL44042.pdf
Title and statement of responsibility and : PARAMETRIC FAULT MODEL FOR LINEAR THRESHOLD LOGIC NETWORKS [Thesis]
 
 
 
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