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Document Type : Latin Dissertation
Language of Document : English
Record Number : 148682
Doc. No : ET20474
Main Entry : CHEN, TING-CHANG
Title Proper : AN INVESTIGATION OF THE SIMULATION PERFORMANCE OF VERILOG FOR LARGE CIRCUITS
Note : This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract : There is no efficient way so far for predicting the simulation time of a largecircuit, which is still the bottleneck of the whole developing process while the time-tomarketfor a large circuit is demanded shorter and shorter whit a requirement of more andmore complex circuits. If the time for simulating a large circuit can be predicted inadvance, it will benefit the design process. The method of prediction for simulation timealso can be used.
Subject : Electericl tess
: برق
electronic file name : TL43610.pdf
Title and statement of responsibility and : AN INVESTIGATION OF THE SIMULATION PERFORMANCE OF VERILOG FOR LARGE CIRCUITS [Thesis]
 
 
 
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