Enabling Techniques for Low Power, High Performance Fractional-N Frequency Synthesizers

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" Enabling Techniques for Low Power, High Performance Fractional-N Frequency Synthesizers "

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	148518
Doc. No	:	ET20310
Main Entry	:	Ashok Swaminathan
Title Proper	:	Enabling Techniques for Low Power, High Performance Fractional-N Frequency Synthesizers
Note	:	This document is digital این مدرک بصورت الکترونیکی می باشد
Abstract	:	Delta-sigma fractional-N phase-locked loops are used to generate high qualityradio-frequency signals for use in wireless applications. To reduce the phase noiseinherent to these systems, a digital-to-analog converter is used to cancel the error introducedby the fractional division process, however matching between the digital-.
Subject	:	Electericl tess
	:	برق
electronic file name	:	TL43437.pdf
Title and statement of responsibility and	:	Enabling Techniques for Low Power, High Performance Fractional-N Frequency Synthesizers [Thesis]